Data transmission is an important application of many integrated circuit devices. Data may be transmitted according to different transmission protocols, and may be transmitted as serial data or parallel data. A clock and data recovery (CDR) circuit is an important block in a receiver system for high-speed serial communications. The CDR circuit may generate a sampling clock with the correct sampling clock phase for data recovery. The quality of the high-speed serial communication link may be sensitive to the sampling clock phase, especially in the presence of jitter and noise. A CDR circuit may be used to control operation of a phase interpolator (“PI”) for generating the sampling clock. A lock condition for the CDR circuit may be used to determine that the sampling clock from the PI is valid. However, lock conditions of the CDR are susceptible to differences between transmitter and receiver reference clock signals. If both ends of a serial link use the same reference clock signal, then the CDR circuit may be relatively simple. However, each end of a serial data transmission link may use a separate, uncorrelated reference clock. If the frequencies of the transmitter and receiver reference clocks are different, then the phase error may change continuously. As the difference in reference clock frequencies increases, the phase error may change more quickly, impacting the data recovery performance.
Accordingly, it would be desirable and useful to provide an improved CDR circuit.